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ISL62871, ISL62872
Data Sheet August 14, 2008 FN6707.0
PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator
The ISL62871 and ISL62872 IC's are Single-Phase Synchronous-Buck PWM voltage regulators featuring Intersil's Robust Ripple Regulator (R3) TechnologyTM. The wide 3.3V to 25V input voltage range is ideal for systems that run on battery or AC-adapter power sources. The ISL62871 and ISL62872 are low-cost solutions for applications requiring dynamically selected slew-rate controlled output voltages. The soft-start and dynamic setpoint slew-rates are capacitor programmed. Voltage identification logic-inputs select two (ISL62871) or four (ISL62872) resistor-programmed setpoint reference voltages that directly set the output voltage of the converter between 0.5V to 1.5V, and up to 3.3V using a feedback voltage divider. Optionally, an external reference such as the DAC output from a microcontroller, can be used by either IC to program the setpoint reference voltage, and still maintain the controlled slew-rate features. Robust integrated MOSFET drivers and Schottky bootstrap diode reduce the implementation area and lower component cost. Intersil's R3 TechnologyTM combines the best features of both fixed-frequency and hysteretic PWM control. The PWM frequency is 300kHz during static operation, becoming variable during changes in load, setpoint voltage, and input voltage when changing between battery and AC-adapter power. The modulators ability to change the PWM switching frequency during these events in conjunction with external loop compensation produces superior transient response. For maximum efficiency, the converter automatically enters diode-emulation mode (DEM) during light-load conditions such as system standby.
Features
* Input Voltage Range: 3.3V to 25V * Output Voltage Range: 0.5V to 3.3V * Output Load up to 30A * Extremely Flexible Output Voltage Programmability - 2-Bit VID (ISL62872) Selects Four Independent Setpoint Voltages - 1-Bit VID (ISL62871) Selects Two Independent Setpoint Voltages - Simple Resistor Programming of Setpoint Voltages - Accepts External Setpoint Reference Such as DAC * 0.75% System Accuracy: -10C to +100C * One Capacitor Programs Soft-start and Setpoint Slew-rate * Fixed 300kHz PWM Frequency in Continuous Conduction * External Compensation Affords Optimum Control Loop Tuning * Automatic Diode Emulation Mode for Highest Efficiency * Integrated High-current MOSFET Drivers and Schottky Boot-Strap Diode for Optimal Efficiency * Choice of Overcurrent Detection Schemes - Lossless Inductor DCR Current Sensing - Precision Resistive Current Sensing * Power-Good Monitor for Soft-Start and Fault Detection * Fault Protection - Undervoltage - Overvoltage - Overcurrent (DCR-Sense or Resistive-Sense Capability) - Over-Temperature Protection - Fault Identification by PGOOD Pull-Down Resistance * Pb-Free (RoHS compliant)
Applications
* Mobile PC Graphical Processing Unit VCC rail * Mobile PC I/O Controller Hub (ICH) VCC rail * Mobile PC Memory Controller Hub (GMCH) VCC rail * Built-in voltage margin for system-level test
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL62871, ISL62872 Pinouts
ISL62872 (20 LD 3.2X1.8 TQFN) TOP VIEW
1 LGATE 20 PVCC
ISL62871 (16 LD 2.6X1.8 TQFN) TOP VIEW
15 LGATE 16 PGND 14 PVCC FB 7 13 VCC 12 BOOT 11 UGATE 10 PHASE 9 OCSET SET0 5 PGOOD 6 VO 8
PGND 2 GND 3 EN 4 VID1 5 VID0 6 SREF 7 SET0 8 SET2 10
19 VCC 18 BOOT 17 UGATE 16 PHASE 15 NC 14 OCSET 13 VO GND 1 EN 2 VID0 3 SREF 4
Ordering Information
PART NUMBER (Note) ISL62872HRUZ ISL62872HRUZ -T* ISL62871HRUZ ISL62871HRUZ -T* PART MARKING GAN GAN GAM GAM TEMP RANGE (C) -10 to +100 -10 to +100 -10 to +100 -10 to +100 PACKAGE (Pb-Free) 20 Ld 3.2x1.8 TQFN 20 Ld 3.2x1.8 TQFN 16 Ld 2.6x1.8 TQFN 16 Ld 2.6x1.8 TQFN PKG. DWG. # L20.3.2x1.8 L20.3.2x1.8 L16.2.6x1.8A L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
PGOOD 11
SET1 9
12 FB
FN6707.0 August 14, 2008
Block Diagram
EN VCC 100k
POR
FAULT
RUN
RUN PWM DRIVER
SHOOT-THROUGH PROTECTION
BOOT UGATE PHASE PVCC
3
FB - EA + VCOMP VW H L IN OTP PWM RUN 100pF VCC gmVIN + - VR VSET Cr SW0 SREF SW1 SET0 SW2 *SET1 SW3 *SET2 - OVP + VID DECODER VID0 *ISL62872 ONLY EXT VREF GND 500mV INT SW4 FB - UVP + FAULT gmVO *VID1 - OCP +
FN6707.0 August 14, 2008
DRIVER
LGATE PGND
ISL62871, ISL62872
+ -
+ -
VO OCSET IOCSET 10F PGOOD
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62872, ISL62871
ISL62871, ISL62872 Application Schematics
RVCC +5V LGATE VIN 3.3V TO 25V CVCC CINC 19 18 17 16 15 14 13 10 11 12 VCC RPGOOD VCC BOOT UGATE PHASE ROCSET NC OCSET VO FB RCOMP CCOMP CBOOT QLS COCSET QHS LO VOUT 0.5V TO 3.3V COC COB CINB
CPVCC PGND GND EN GPIO VID1 VID0 SREF SET0 SET1 2 3 4 5 6 7 8 9
1
20
PVCC
RO
RSET1 CSOFT
RSET2
RSET3 RSET4
PGOOD
SET2
GPIO
FIGURE 2. ISL62872 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
RVCC +5V LGATE VIN 3.3V TO 25V CVCC CINC 19 18 17 16 15 14 13 10 11 12 VCC RPGOOD VCC BOOT UGATE LO PHASE ROCSET NC OCSET VO FB RCOMP CCOMP CBOOT QLS COCSET RSNS QHS VOUT 0.5V TO 3.3V COC COB CINB
CPVCC PGND GND EN GPIO VID1 VID0 SREF SET0 SET1 2 3 4 5 6 7 8 9
1
20
PVCC
ROFS
RFB
RO
RSET1 CSOFT
RSET2
RSET3 RSET4
PGOOD
SET2
GPIO
FIGURE 3. ISL62872 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
4
ROFS
RFB
FN6707.0 August 14, 2008
ISL62871, ISL62872 Application Schematics (Continued)
RVCC +5V CPVCC LGATE PGND PVCC CVCC VIN 3.3V TO 25V VCC CINC BOOT UGATE LO PHASE ROCSET OCSET CBOOT QLS COCSET QHS VOUT 0.5V TO 3.3V COC COB CINB
16
15
14 7 FB
GND EN GPIO VID0 SREF
1 2 3 4 5 6
12 11 10 9 8 VO
RSET1 CSOFT
PGOOD
SET0
13
RO RCOMP CCOMP
VCC RPGOOD
RSET2
ROFS
RFB
GPIO
FIGURE 4. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
RVCC +5V CPVCC LGATE PGND PVCC CVCC VIN 3.3V TO 25V VCC CINC BOOT UGATE LO PHASE ROCSET OCSET CBOOT QLS COCSET RSNS QHS VOUT 0.5V TO 3.3V COC COB CINB
16
15
14 7 FB
GND EN GPIO VID0 SREF
1 2 3 4 5 6
12 11 10 9 8 VO
RSET1 CSOFT
PGOOD
SET0
13
RO RCOMP CCOMP
VCC RPGOOD
RSET2
ROFS
RFB
GPIO
FIGURE 5. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
5
FN6707.0 August 14, 2008
ISL62871, ISL62872 Application Schematics (Continued)
RVCC +5V LGATE PVCC CVCC CINC 19 18 17 16 15 14 13 10 11 12 VCC BOOT UGATE PHASE ROCSET NC OCSET VO FB RCOMP CCOMP CBOOT QLS COCSET QHS LO VOUT 0.5V TO 3.3V COC COB CINB
VIN 3.3V TO 25V
CPVCC PGND GND GPIO EN VID1 EXT_REF CSOFT VID0 SREF SET0 SET1 VCC RPGOOD 2 3 4 5 6 7 8 9
1
20
RO
SET2
PGOOD
GPIO
FIGURE 6. ISL62872 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
RVCC +5V CPVCC LGATE PGND PVCC CVCC VIN 3.3V TO 25V VCC CINC BOOT UGATE LO PHASE ROCSET OCSET CBOOT QLS COCSET QHS VOUT 0.5V TO 3.3V COC COB CINB
16
15
14
GND GPIO EXT_REF CSOFT EN VID0 SREF
1 2 3 4 5 6 7
12 11 10 9 8
PGOOD
SET0
FB
VO
13
ROFS
RFB
RO RCOMP CCOMP
VCC RPGOOD
ROFS
GPIO
RFB
FIGURE 7. ISL62871 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
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FN6707.0 August 14, 2008
ISL62871, ISL62872
Absolute Maximum Ratings
VCC, PVCC, PGOOD to GND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V EN, SET0, SET1, SET2, VO, VID0, VID1, FB, OCSET, SREF. . . . . . . -0.3V to GND, VCC + 0.3V BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V GND -8V (<20ns Pulse Width, 10J) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 20 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . 84 16 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . 84 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10C to +100C Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . 3.3V to 25V VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER VCC and PVCC VCC Input Bias Current VCC Shutdown Current PVCC Shutdown Current VCC POR THRESHOLD Rising VCC POR Threshold Voltage Falling VCC POR Threshold Voltage REGULATION Reference Voltage System Accuracy PWM Switching Frequency VO VO Input Voltage Range VO Input Impedance VO Reference Offset Current VO Input Leakage Current ERROR AMPLIFIER FB Input Bias Current SREF SREF Operating Voltage Range Soft-Start Current Voltage Step Current
IVCC IVCCoff IPVCCoff
EN = 5V, VCC = 5V, FB = 0.55V, SREF-
1.1 0.1 0.1
1.5 1.0 1.0
mA A A
VVCC_THR V
VCC_THF
4.40 4.10
4.49 4.22
4.60 4.35
V V
VREF(int) VID0 = VID1 = GND, PWM Mode = CCM
-0.75
0.50 -
+0.75
V %
FSW
PWM Mode = CCM
270
300
330
kHz
VVO RVO IVOSS IVOoff EN = 5V VENTHR < EN, SREF = Soft-Start Mode EN = GND, VO = 3.6V
0 -
600 10 .1
3.6 -
V k A A
IFB
EN = 5V, FB = 0.50V
-20
-
+50
nA
VSREF ISS IVS
Nominal SREF Setting With 1% Resistors SREF = Soft-Start Mode SREF = Setpoint-Stepping Mode
0.5 10 60
20 100
1.5 30 140
V A A
7
FN6707.0 August 14, 2008
ISL62871, ISL62872
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER EXTERNAL REFERENCE EXTREF Operating Voltage Range EXTREF Accuracy POWER GOOD PGOOD Pull-down Impedance
VEXT
SET0 = VCC
0 -0.5
-
1.5 +0.5
V %
VEXT_OFS SET0 = VCC, VID0 = 0V to 1.5V
RPG_SS RPG_UV RPG_OV RPG_OC
PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5V
75 75 50 25 -
95 95 65 35 0.1 5.0
150 150 90 50 1.0 -
A mA
PGOOD Leakage Current PGOOD Maximum Sink Current (Note 2) GATE DRIVER UGATE Pull-Up Resistance (Note 2) UGATE Source Current (Note 2) UGATE Sink Resistance (Note 2) UGATE Sink Current (Note 2) LGATE Pull-Up Resistance (Note 2) LGATE Source Current (Note 2) LGATE Sink Resistance (Note 2) LGATE Sink Current (Note 2) UGATE to LGATE Deadtime LGATE to UGATE Deadtime PHASE PHASE Input Impedance BOOTSTRAP DIODE Forward Voltage Reverse Leakage CONTROL INPUTS EN High Threshold Voltage EN Low Threshold Voltage EN Input Bias Current EN Leakage Current VID<0,1> High Threshold Voltage VID<0,1> Low Threshold Voltage VID<0,1> Input Bias Current VID<0,1> Leakage Current PROTECTION OCP Threshold Voltage OCP Reference Current OCSET Input Resistance OCSET Leakage Current UVP Threshold Voltage
IPG IPG_max
RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR
200mA Source Current UGATE - PHASE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current LGATE - GND = 2.5V 250mA Sink Current LGATE - PGND = 2.5V UGATE falling to LGATE rising, no load LGATE falling to UGATE rising, no load
-
1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 21 21
1.5 1.5 1.5 0.9 -
A A A A ns ns
RPHASE
-
33
-
k
VF IR
PVCC = 5V, IF = 2mA VR = 25V
-
0.58 0.2
-
V A
VENTHR VENTHF IEN IENoff VVIDTHR VVIDTHF IVID IVIDoff EN = 5V, VVID = 1V EN = 5V EN = GND
2.0 1.5 0.6 -
2.0 0.1 0.5 0
1.0 2.5 1.0 0.5 -
V V A A V V A A
VOCPTH IOCP ROCSET IOCSET VUVTH
VOCSET - VO EN = 5.0V EN = 5.0V EN = GND VFB = %VSREF
-1.75 9.0 81
10 600 0 84
1.75 11 87
mV A k A %
8
FN6707.0 August 14, 2008
ISL62871, ISL62872
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL VOVRTH VOVFTH TOTRTH TOTHYS VFB = %VSREF VFB = %VSREF TEST CONDITIONS MIN 113 100 TYP 116 102 150 25 MAX 120 106 UNIT % % C C
PARAMETER OVP Rising Threshold Voltage OVP Falling Threshold Voltage OTP Rising Threshold Temperature (Note 2) OTP Hysteresis (Note 2) NOTE:
2. Limits established by characterization and are not production tested.
ISL62872 Functional Pin Descriptions
LGATE (Pin 1)
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
SET2 (Pin 10)
Voltage set-point programming resistor input. See Figure 8 on page 12 for resistor connection.
PGOOD (Pin 11)
Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. The pull-down resistance between the PGOOD pin and the GND pin identifies which protective fault has shut down the regulator. See Table 3 on page 16.
PGND (Pin 2)
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
GND (Pin 3)
IC ground for bias supply and signal reference.
FB (Pin 12)
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. The control loop compensation network connects between the FB pin and the converter output. See Figure 13 on page 17.
EN (Pin 4)
Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the soft-start sequence.
VID1 (Pin 5)
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four setpoint reference voltages.
VO (Pin 13)
Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. See Figure 10 on page 14.
VID0 (Pin 6)
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among four setpoint reference voltages. External reference input when enabled by connecting the SET0 pin to the VCC pin.
OCSET (Pin 14)
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. See Figure 10 on page 14.
SREF (Pin 7)
Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage programming resistor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. See Figure 8 page 12 for capacitor and resistor connections.
NC (Pin 15)
No internal connection. Pin 15 should be connected to the GND pin.
PHASE (Pin 16)
Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3 modulator. Inductor current polarity detector input. Connect to junction of output inductor, high-side MOSFET, and low-side MOSFET. See Figures 2 and 3 on page 4.
SET0 (Pin 8)
Voltage set-point programming resistor input. See Figure 8 on page 12 for resistor connection.
SET1 (Pin 9)
Voltage set-point programming resistor input. See Figure 8 on page 12 for resistor connection.
UGATE (Pin 17)
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
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FN6707.0 August 14, 2008
ISL62871, ISL62872
BOOT (Pin 18)
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin.
VO (Pin 8)
Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. See Figure 10 on page 14.
OCSET (Pin 9)
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. See Figure 10 on page 14.
VCC (Pin 19)
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1F MLCC to the GND pin. See "Application Schematics" (Figures 2 and 3) on page 4.
PHASE (Pin 10)
Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3 modulator. Inductor current polarity detector input. Connect to junction of output inductor, high-side MOSFET, and low-side MOSFET. See "Application Schematics" (Figures 4 and 5) on page 5.
PVCC (Pin 20)
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10F MLCC to the PGND pin. See "Application Schematics" (Figures 2 and 3) on page 4.
UGATE (Pin 11)
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
ISL62871 Functional Pin Descriptions
GND (Pin 1)
IC ground for bias supply and signal reference.
BOOT (Pin 12)
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin.
EN (Pin 2)
Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the soft-start sequence.
VID0 (Pin 3)
Logic input for setpoint voltage selector. Use to select between the two setpoint reference voltages. External reference input when enabled by connecting the SET0 pin to the VCC pin.
VCC (Pin 13)
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1F MLCC to the GND pin. See "Application Schematics" (Figures 4 and 5) on page 5.
PVCC (Pin 14)
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10F MLCC to the PGND pin. See "Application Schematics" (Figures 4 and 5) on page 5.
SREF (Pin 4)
Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage programming resistor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. See Figure 9 on page 12 for capacitor and resistor connections.
LGATE (Pin 15)
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
SET0 (Pin 5)
Voltage set-point programming resistor input. See Figure 9 on page 12 for resistor connection.
PGND (Pin 16)
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
PGOOD (Pin 6)
Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. The pull-down resistance between the PGOOD pin and the GND pin identifies which protective fault has shut down the regulator. See Table 3 on page 16.
Setpoint Reference Voltage Programming
Voltage identification (VID) pins select user-programmed setpoint reference voltages that appear at the SREF pin. The converter is in regulation when the FB pin voltage (VFB) equals the SREF pin voltage (VSREF.) The IC measures VFB and VSREF relative to the GND pin, not the PGND pin. The setpoint reference voltages use the naming convention
FB (Pin 7)
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. The control loop compensation network connects between the FB pin and the converter output. See Figure 13 on page 17. 10
FN6707.0 August 14, 2008
ISL62871, ISL62872
VSET(x) where (x) is the first, second, third, or fourth setpoint reference voltage where: - VSET1 < VSET2 < VSET3 < VSET4 - VOUT1 < VOUT2 < VOUT3 < VOUT4 The VSET1 setpoint is fixed at 500mV because it corresponds to the closure of internal switch SW0 that configures the VSET amplifier as a unity-gain voltage follower for the 500mV voltage reference VREF. A feedback voltage-divider network may be required to achieve the desired reference voltages. Using the feedback voltage-divider allows the maximum output voltage of the converter to be higher than the 1.5V maximum setpoint reference voltage that can be programmed on the SREF pin. Likewise, the feedback voltage-divider allows the minimum output voltage of the converter to be higher than the fixed 500mV setpoint reference voltage of VSET1. Scale the voltage-divider network such that the voltage VFB equals the voltage VSREF when the converter output voltage is at the desired level. The voltage-divider relation is given in Equation 1:
R OFS V FB = V OUT --------------------------------R +R
FB
The setpoint reference voltages are programmed with resistors that use the naming convention RSET(x) where (x) is the first, second, third, or fourth programming resistor connected in series starting at the SREF pin and ending at the GND pin. When one of the internal switches closes, it connects the inverting input of the VSET amplifier to a specific node among the string of RSET programming resistors. All the resistors between that node and the SREF pin serve as the feedback impedance RF of the VSET amplifier. Likewise, all the resistors between that node and the GND pin serve as the input impedance RIN of the VSET amplifier. Equation 4 gives the general form of the gain equation for the VSET amplifier:
RF V SET ( X ) = V REF 1 + --------- R IN (EQ. 4)
Where: - VREF is the 500mV internal reference of the IC - VSET(x) is the resulting setpoint reference voltage that appears at the SREF pin
(EQ. 1)
Calculating Setpoint Voltage Programming Resistor Values for ISL62872
TABLE 1. ISL62872 VID TRUTH TABLE
OFS
Where: - VFB = VSREF - RFB is the loop-compensation feedback resistor that connects from the FB pin to the converter output - ROFS is the voltage-scaling programming resistor that connects from the FB pin to the GND pin The attenuation of the feedback voltage divider is written as:
R OFS V SREF ( lim ) K = ------------------------------ = --------------------------------V OUT ( lim ) R FB + R OFS (EQ. 2)
VID STATE VID1 1 1 0 0 VID0 1 0 1 0 CLOSE SW0 SW1 SW2 SW3
RESULT VSREF VSET1 VSET2 VSET3 VSET4 VOUT VOUT1 VOUT2 VOUT3 VOUT4
Where: - K is the attenuation factor - VSREF(lim) is the VSREF voltage setpoint of either 500mV or 1.50V - VOUT(lim) is the output voltage of the converter when VSREF = VSREF(lim) Since the voltage-divider network is in the feedback path, all output voltage setpoints will be attenuated by K, so it follows that all of the setpoint reference voltages will be attenuated by K. It will be necessary then to include the attenuation factor K in all the calculations for selecting the RSET programming resistors. The value of offset resistor ROFS can be calculated only after the value of loop-compensation resistor RFB has been determined. The Calculation of ROFS is written as Equation 3:
V SET ( x ) R FB R OFS = ------------------------------------------V OUT - V SET ( x ) (EQ. 3)
First, determine the attenuation factor K. Next, assign an initial value to RSET4 of approximately 100k then calculate RSET1, RSET2, and RSET3 using Equations 5, 6, and 7 respectively. The equation for the value of RSET1 is written as Equation 5:
R SET4 KV SET4 ( KV SET2 - V REF ) R SET1 = --------------------------------------------------------------------------------------------------V REF KV SET2 (EQ. 5)
The equation for the value of RSET2 is written as Equation 6:
R SET4 KV SET4 ( KV SET3 - KV SET2 ) R SET2 = ----------------------------------------------------------------------------------------------------------KV SET2 KV SET3 (EQ. 6)
The equation for the value of RSET3 is written as Equation 7:
R SET4 ( KV SET4 - KV SET3 ) R SET3 = ------------------------------------------------------------------------------KV SET3 (EQ. 7)
The sum of all the programming resistors should be approximately 300k as shown in Equation 8 otherwise adjust the value of RSET4 and repeat the calculations.
R SET1 + R SET2 + R SET3 + R SET4 300k (EQ. 8)
Equations 9, 10, 11 and 12 give the specific VSET gain equations for the ISL62872 setpoint reference voltages.
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The ISL62872 VSET1 setpoint is written as Equation 9:
V SET1 = V REF (EQ. 9)
The equation for the value of RSET1 is written as Equation 13:
KV SET2 R SET1 = R SET2 ---------------------- - 1 V REF (EQ. 13)
The ISL62872 VSET2 setpoint is written as Equation 10:
R SET1 V SET2 = V REF 1 + -------------------------------------------------------------------- R SET2 + R SET3 + R SET4 (EQ. 10)
The ISL62872 VSET3 setpoint is written as Equation 11:
R SET1 + R SET2 V SET3 = V REF 1 + ------------------------------------------- R SET3 + R SET4 (EQ. 11)
The sum of RSET1 and RSET2 programming resistors should be approximately 300k as shown in Equation 14 otherwise adjust the value of RSET2 and repeat the calculations.
R SET1 + R SET2 300k (EQ. 14)
Equations 15 and 16 give the specific VSET gain equations for the ISL62871 setpoint reference voltages. The ISL62871 VSET1 setpoint is written as Equation 15:
V SET1 = V REF (EQ. 15)
The ISL62872 VSET4 setpoint is written as Equation 12:
R SET1 + R SET2 + R SET3 V SET4 = V REF 1 + -------------------------------------------------------------------- R SET4 (EQ. 12)
The ISL62871 VSET2 setpoint is written as Equation 16:
R SET1 V SET2 = V REF 1 + ------------------ R SET2 (EQ. 16)
VOUT
RFB ROFS
FB
- EA +
VCOMP VOUT RFB ROFS
+ VSET - SW0
VREF 500mV
FB
- EA +
VCOMP
VREF VSET - SW0 +
SREF CSOFT RSET1
SET0
SW1 CSOFT RSET1
SREF
RSET2
SET1
SW2
SET0
SW1
RSET3
SET2
SW3
FIGURE 8. ISL62872 VOLTAGE PROGRAMMING CIRCUIT
Component Selection for ISL62871 Setpoint Voltage Programming Resistors
TABLE 2. ISL62871 VID TRUTH TABLE STATE VID0 1 0 CLOSE SW0 SW1 RESULT VSREF VSET1 VSET2 VOUT VOUT1 VOUT2
First, determine the attenuation factor K. Next, assign an initial value to RSET2 of approximately 150k then calculate RSET1 using Equation 13.
RSET4
FIGURE 9. ISL62871 VOLTAGE PROGRAMMING CIRCUIT
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External Setpoint Reference
The IC can use an external setpoint reference voltage as an alternative to VID-selected, resistor-programmed setpoints. This is accomplished by removing all setpoint programming resistors, connecting the SET0 pin to the VCC pin, and feeding the external setpoint reference voltage to the VID0 pin. When SET0 and VCC are tied together, the following internal reconfigurations take place: - VID0 pin opens its 500nA pull-down current sink - Reference source selector switch SW4 moves from INT position (internal 500mV) to EXT position (VID0 pin) - VID1 pin is disabled The converter will now be in regulation when the voltage on the FB pin equals the voltage on the VID0 pin. As with resistor-programmed setpoints, the reference voltage range on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3 beginning on page 11 should it become necessary to implement an output voltage-divider network to make the external setpoint reference voltage compatible with the 500mV to 1.5V constraint. Where: - ISS is the soft-start current source at the 20A limit - VSTART-UP is the setpoint reference voltage selected by the state of the VID inputs at the time EN is asserted - RT is the sum of the RSET programming resistors The end of soft-start is detected by ISS tapering off when capacitor CSOFT charges to the designated VSET voltage reference setpoint. The SSOK flag is set, the PGOOD pin goes high, and the ISS current source changes over to the voltage-step current source IVS which has a current limit of 100A. Whenever the VID inputs or the external setpoint reference, programs a different setpoint reference voltage, the IVS current source charges or discharges capacitor CSOFT to that new level at 100A. Once CSOFT charges to the selected setpoint voltage, the IVS current source comes out of the 100A current limit and decays to the static value set by VSREF / RT. The elapsed time to charge CSOFT to the new voltage is called the voltage-step delay tVS and is given by Equation 19:
( V NEW - V OLD ) t VS = ( I VS C SOFT ) LN(1 - -------------------------------------------) I R
VS T
(EQ. 19)
Soft-Start and Voltage-Step Delay
Circuit Description
When the voltage on the VCC pin has ramped above the rising power-on reset voltage VVCC_THR, and the voltage on the EN pin has increased above the rising enable threshold voltage VENTHR, the SREF pin releases its discharge clamp and enables the reference amplifier VSET. The soft-start current ISS is limited to 20A and is sourced out of the SREF pin into the parallel RC network of capacitor CSOFT and resistance RT. The resistance RT is the sum of all the series connected RSET programming resistors and is written as Equation 17:
R T = R SET1 + R SET2 + ...R SET ( n ) (EQ. 17)
Where: - IVS is the 100A setpoint voltage-step current - VNEW is the new setpoint voltage selected by the VID inputs - VOLD is the setpoint voltage that VNEW is changing from - RT is the sum of the RSET programming resistors
Component Selection For CSOFT Capacitor
Choosing the CSOFT capacitor to meet the requirements of a particular soft-start delay tSS is calculated with Equation 20, which is written as:
- t SS C SOFT = --------------------------------------------------------------------V START-UP R T LN(1 - ----------------------------- ) I SS R T (EQ. 20)
The voltage on the SREF pin rises as ISS charges CSOFT to the voltage reference setpoint selected by the state of the VID inputs at the time the EN pin is asserted. The regulator controls the PWM such that the voltage on the FB pin tracks the rising voltage on the SREF pin. Once CSOFT charges to the selected setpoint voltage, the ISS current source comes out of the 20A current limit and decays to the static value set by VSREF / RT. The elapsed time from when the EN pin is asserted to when VSREF has reached the voltage reference setpoint is the soft-start delay tSS which is given by Equation 18:
V START-UP t SS = - ( I SS C SOFT ) LN(1 - ----------------------------- ) I R
SS T
Where: tSS is the soft-start delay ISS is the soft-start current source at the 20A limit VSTART-UP is the setpoint reference voltage selected by the state of the VID inputs at the time EN is asserted - RT is the sum of the RSET programming resistors Choosing the CSOFT capacitor to meet the requirements of a particular voltage-step delay tVS is calculated with Equation 21, which is written as:
- t VS C SOFT = ----------------------------------------------------------------------------V NEW - V OLD R T LN(1 - -------------------------------------- ) I VS R T (EQ. 21)
(EQ. 18)
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Where: - tVS is the voltage-step delay - VNEW is the new setpoint voltage - VOLD is the setpoint voltage that VNEW is changing from - IVS is the 100A setpoint voltage-step current; positive when VNEW > VOLD, negative when VNEW < VOLD - RT is the sum of the RSET programming resistors
Component Selection For ROCSET and CSEN
The value of ROCSET is calculated with Equation 25, which is written as:
I OC DCR R OCSET = --------------------------I OCSET (EQ. 25)
Where: - ROCSET () is the resistor used to program the overcurrent setpoint - IOC is the output DC load current that will activate the OCP fault detection circuit - DCR is the inductor DC resistance For example, if IOC is 20A and DCR is 4.5m, the choice of ROCSET is = 20A x 4.5m/10A = 9k. Resistor ROCSET and capacitor CSEN form an R-C network to sense the inductor current. To sense the inductor current correctly not only in DC operation, but also during dynamic operation, the R-C network time constant ROCSET CSEN needs to match the inductor time constant L/DCR. The value of CSEN is then written as Equation 26:
L C SEN = ----------------------------------------R OCSET DCR (EQ. 26)
Fault Protection
Overcurrent
The overcurrent protection (OCP) setpoint is programmed with resistor ROCSET which is connected across the OCSET and PHASE pins. Resistor RO is connected between the VO pin and the actual output voltage of the converter. During normal operation, the VO pin is a high impedance path, therefore there is no voltage drop across RO. The value of resistor RO should always match the value of resistor ROCSET
L DCR PHASE IL VDCR CSEN VO
+
ROCSET
_
CO
For example, if L is 1.5H, DCR is 4.5m, and ROCSET is 9k, the choice of CSEN = 1.5H/(9k x 4.5m) = 0.037F. When an OCP fault is declared, the PGOOD pin will pull-down to 35 and latch off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF.
10
OCSET
+ VROCSET
RO
_
VO
FIGURE 10. OVERCURRENT PROGRAMMING CIRCUIT
Overvoltage
The OVP fault detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2s. For example, if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to rise above the typical VOVRTH threshold of 116% for more than 2s in order to trip the OVP fault latch. In numerical terms, that would be 116% x 1.0V = 1.16V. When an OVP fault is declared, the PGOOD pin will pull-down to 65 and latch-off the converter. The OVP fault will remain latched until VCC has decayed below the falling POR threshold voltage V VCC_THF. An OVP fault cannot be reset by pulling the EN pin below the falling EN threshold voltage VENTHF. Although the converter has latched-off in response to an OVP fault, the LGATE gate-driver output will retain the ability to toggle the low-side MOSFET on and off, in response to the output voltage transversing the VOVRTH and VOVFTH thresholds. The LGATE gate-driver will turn-on the low-side MOSFET to discharge the output voltage, protecting the load. The LGATE gate-driver will turn-off the low-side MOSFET once the FB pin voltage is lower than the falling overvoltage threshold VOVRTH for more than 2s. The falling overvoltage threshold VOVFTH is typically 102%. That
Figure 10 shows the overcurrent set circuit. The inductor consists of inductance L and the DC resistance DCR. The inductor DC current IL creates a voltage drop across DCR, which is given by Equation 22:
V DCR = I L DCR (EQ. 22)
The IOCSET current source sinks 10A into the OCSET pin, creating a DC voltage drop across the resistor ROCSET, which is given by Equation 23:
V ROCSET = 10A R OCSET (EQ. 23)
The DC voltage difference between the OCSET pin and the VO pin, which is given by Equation 24:
V OCSET - V VO = V DCR - V ROCSET = I L DCR - I OCSET R OCSET (EQ. 24)
The IC monitors the voltage of the OCSET pin and the VO pin. When the voltage of the OCSET pin is higher than the voltage of the VO pin for more than 10s, an OCP fault latches the converter off.
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means if the FB pin voltage falls below 102% x 1.0V = 1.02V for more than 2s, the LGATE gate-driver will turn off the low-side MOSFET. If the output voltage rises again, the LGATE driver will again turn on the low-side MOSFET when the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2s. By doing so, the IC protects the load when there is a consistent overvoltage condition. of the transient and work in concert with the error amplifier VERR to maintain output voltage regulation. Once the transient has dissipated and the control loop has recovered, the PWM frequency returns to the nominal static 300KHz.
Modulator
The R3 modulator synthesizes an AC signal VR, which is an analog representation of the output inductor ripple current. The duty-cycle of VR is the result of charge and discharge current through a ripple capacitor CR. The current through CR is provided by a transconductance amplifier gm that measures the input voltage (VIN) at the PHASE pin and output voltage (VOUT) at the VO pin. The positive slope of VR can be written as Equation 27:
V RPOS = ( g m ) ( V IN - V OUT ) C R (EQ. 27)
Undervoltage
The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold VUVTH for more than 2s. For example if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to fall below the typical VUVTH threshold of 84% for more than 2s in order to trip the UVP fault latch. In numerical terms, that would be 84% x 1.0V = 0.84V. When a UVP fault is declared, the PGOOD pin will pull-down to 95 and latch-off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF.
The negative slope of VR can be written as Equation 28:
V RNEG = g m V OUT C R (EQ. 28)
Where, gm is the gain of the transconductance amplifier. A window voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating an envelope into which the ripple voltage VR is compared. The amplitude of VW is controlled internally by the IC. The VR, VCOMP, and VW signals feed into a window comparator in which VCOMP is the lower threshold voltage and VW is the higher threshold voltage. Figure 11 shows PWM pulses being generated as VR traverses the VW and VCOMP thresholds. The PWM switching frequency is proportional to the slew rates of the positive and negative slopes of VR; it is inversely proportional to the voltage between VW and VCOMP.
Over-Temperature
When the temperature of the IC increases above the rising threshold temperature TOTRTH, it will enter the OTP state that suspends the PWM, forcing the LGATE and UGATE gate-driver outputs low. The status of the PGOOD pin does not change nor does the converter latch-off. The PWM remains suspended until the IC temperature falls below the hysteresis temperature TOTHYS at which time normal PWM operation resumes. The OTP state can be reset if the EN pin is pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage V VCC_THF. All other protection circuits remain functional while the IC is in the OTP state. It is likely that the IC will detect an UVP fault because in the absence of PWM, the output voltage decays below the undervoltage threshold VUVTH.
RIPPLE CAPACITOR VOLTAGE CR
WINDOW VOLTAGE VW
Theory of Operation
The modulator features Intersil's R3 Robust-RippleRegulator technology, a hybrid of fixed frequency PWM control and variable frequency hysteretic control. The PWM frequency is maintained at 300KHz under static continuous-conduction-mode operation within the entire specified envelope of input voltage, output voltage, and output load. If the application should experience a rising load transient and/or a falling line transient such that the output voltage starts to fall, the modulator will extend the on-time and/or reduce the off-time of the PWM pulse in progress. Conversely, if the application should experience a falling load transient and/or a rising line transient such that the output voltage starts to rise, the modulator will truncate the on-time and/or extend the off-time of the PWM pulse in progress. The period and duty cycle of the ensuing PWM pulses are optimized by the R3 modulator for the remainder
ERROR AMPLIFIER VOLTAGE VCOMP
PWM
FIGURE 11. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling diode to maintain uninterrupted current conduction through the output inductor when the high-side MOSFET switches off for the balance of the PWM switching cycle. Low conversion efficiency as a result of the conduction loss of the diode
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makes this an unattractive option for all but the lowest current applications. Efficiency is dramatically improved when the free-wheeling diode is replaced with a MOSFET that is turned on whenever the high-side MOSFET is turned off. This modification to the standard DC/DC buck regulator is referred to as synchronous rectification, the topology implemented by the ISL62871 and ISL62872 controllers.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the VENTHR rising threshold voltage, the following criteria must be met: - VPVCC is at least equivalent to the VCC rising power-on reset voltage VVCC_THR - VVIN must be 3.3V or the minimum required by the application
Diode Emulation
The polarity of the output inductor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. The DC component of the inductor current is positive, but the AC component known as the ripple current, can be either positive or negative. Should the sum of the AC and DC components of the inductor current remain positive for the entire switching period, the converter is in continuous-conduction-mode (CCM.) However, if the inductor current becomes negative or zero, the converter is in discontinuous-conduction-mode (DCM.) Unlike the standard DC/DC buck regulator, the synchronous rectifier can sink current from the output filter inductor during DCM, reducing the light-load efficiency with unnecessary conduction loss as the low-side MOSFET sinks the inductor current. The ISL62871 and ISL62872 controllers avoid the DCM conduction loss by making the low-side MOSFET emulate the current-blocking behavior of a diode. This smart-diode operation called diode-emulation-mode (DEM) is triggered when the negative inductor current produces a positive voltage drop across the rDS(ON) of the low-side MOSFET for eight consecutive PWM cycles while the LGATE pin is high. The converter will exit DEM on the next PWM pulse after detecting a negative voltage across the rDS(ON) of the low-side MOSFET. It is characteristic of the R3 architecture for the PWM switching frequency to decrease while in DCM, increasing efficiency by reducing unnecessary gate-driver switching losses. The extent of the frequency reduction is proportional to the reduction of load current. Upon entering DEM, the PWM frequency is forced to fall approximately 30% by forcing a similar increase of the window voltage V W. This measure is taken to prevent oscillating between modes at the boundary between CCM and DCM. The 30% increase of VW is removed upon exit of DEM, forcing the PWM switching frequency to jump back to the nominal CCM value.
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller can be enabled by pulling the EN pin voltage above the input-high threshold VENTHR. Approximately 20s later, the voltage at the SREF pin begins slewing to the designated VID set-point. The converter output voltage at the FB feedback pin follows the voltage at the SREF pin. During soft-start, The regulator always operates in CCM until the soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of supplying regulated voltage. The PGOOD pin is an undefined impedance if the VCC pin has not reached the rising POR threshold VVCC_THR, or if the VCC pin is below the falling POR threshold VVCC_THF. The PGOOD pull-down resistance corresponds to a specific protective fault, thereby reducing troubleshooting time and effort. Table 3 maps the pull-down resistance of the PGOOD pin to the corresponding fault status of the controller.
TABLE 3. PGOOD PULL-DOWN RESISTANCE CONDITION VCC Below POR Soft-Start or Undervoltage Overvoltage Overcurrent PGOOD RESISTANCE Undefined 95 65 35
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver outputs. The LGATE pin drives the low-side MOSFET of the converter while the UGATE pin drives the high-side MOSFET of the converter. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET experiences long conduction times. In this environment, the low-side MOSFETs require exceptionally low rDS(ON) and tend to have large parasitic charges that conduct transient currents within the devices in response to high dv/dt switching present at the phase node. The drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the VGS(th) of the device can be exceeded and turned on. For this reason the LGATE driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the MOSFETs gate voltage below VGS(th).
Power-On Reset
The IC is disabled until the voltage at the VCC pin has increased above the rising power-on reset (POR) threshold voltage VVCC_THR. The controller will become disabled when the voltage at the VCC pin decreases below the falling POR threshold voltage VVCC_THF. The POR detector has a noise filter of approximately 1s.
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Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 12 is extended by the additional period that the falling gate voltage remains above the 1V threshold. The high-side gate-driver output voltage is measured across the UGATE and PHASE pins while the low-side gate-driver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is supplied by a boot-strap capacitor connected across the BOOT and PHASE pins. The capacitor is charged each time the phase node voltage falls a diode drop below PVCC such as when the low-side MOSFET is turned on.
CINT = 100pF RCOMP CCOMP
EA COMP
RFB FB ROFS VOUT
+
SREF
FIGURE 13. COMPENSATION REFERENCE CIRCUIT
UGATE 1V 1V
The LC output filter has a double pole at its resonant frequency that causes rapid phase change. The R3 modulator used in the IC makes the LC output filter resemble a first order system in which the closed loop stability can be achieved with the recommended Type-II compensation network. Intersil provides a PC-based tool that can be used to calculate compensation network component values and help simulate the loop frequency response.
General Application Design Guide
This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts.
1V
1V
LGATE
FIGURE 12. GATE DRIVER ADAPTIVE SHOOT-THROUGH
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is expressed in Equation 30:
VO D = --------V IN (EQ. 30)
Compensation Design
Figure 13 shows the recommended Type-II compensation circuit. The FB pin is the inverting input of the error amplifier. The COMP signal, the output of the error amplifier, is inside the chip and unavailable to users. CINT is a 100pF capacitor integrated inside the IC, connecting across the FB pin and the COMP signal. RFB, RCOMP, CCOMP and CINT form the Type-II compensator. The frequency domain transfer function is given by Equation 29:
1 + s ( R FB + R COMP ) C COMP G COMP ( s ) = -------------------------------------------------------------------------------------------------------------- (EQ. 29) s R FB C INT ( 1 + s R COMP C )
COMP
The output inductor peak-to-peak ripple current is expressed in Equation 31:
VO ( 1 - D ) I P-P = -----------------------------F SW L (EQ. 31)
A typical step-down DC/DC converter will have an IPP of 20% to 40% of the maximum DC output load current. The value of IP-P is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated using Equation 32:
P COPPER = I LOAD DCR
2
(EQ. 32)
Where, ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause 17
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destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance CO into which ripple current IP-P can flow. Current IP-P develops a corresponding ripple voltage VP-P across CO, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages are expressed in Equations 33 and 34:
V ESR = I P-P E SR I P-P V C = -------------------------------8 CO F (EQ. 33)
In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET.
NORMALIZED INPUT RMS RIPPLE CURRENT 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 x=0 x = 0.25 x = 0.50 x = 0.75 x=1
(EQ. 34)
SW
If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VP-P is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be considered. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IP-P is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases.
DUTY CYCLE
FIGURE 14. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. We selected the bootstrap capacitor breakdown voltage to be at least 10V. Although the theoretical maximum voltage of the capacitor is PVCC-VDIODE (voltage drop across the boot diode), large excursions below ground by the phase node requires we select a capacitor with at least a breakdown rating of 10V. The bootstrap capacitor can be chosen from Equation 37:
Q GATE C BOOT ----------------------V BOOT (EQ. 37)
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. Figure 14 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as Equation 35:
2 2D 2 ( I MAX ( D - D ) ) + x I MAX ----- 12 I IN_RMS = ---------------------------------------------------------------------------------------------------I MAX
Where: - QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET - VBOOT is the maximum decay across the BOOT capacitor As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is 0.15F. A good quality ceramic capacitor such as X7R or X5R is recommended.
(EQ. 35)
Where: - IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter Duty cycle is written as Equation 36:
VO D = ------------------------V IN EFF (EQ. 36)
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.
2.0 1.8 1.6 CBOOT_CAP (F 1.4 1.2 1.0 0.8 0.6
nC 50
1000 900 800 700 POWER (mW) 600 500 400 300 200 100 0.2 0.3 0.4 0.5 0.6 0.7 DVBOOT_CAP (V) 0.8 0.9 1.0 0 0
QU =100nC QL =200nC
QU =50nC QL =100nC
QU =50nC QL=50nC
QU =20nC QL=50nC
QGATE = 100nC
0.4 0.2 20nC
0.0 0.0
0.1
200
400
600
800 1k
1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 15. BOOT CAPACITANCE vs BOOT RIPPLE VOLTAGE
FIGURE 16. POWER DISSIPATION vs FREQUENCY
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125C. When designing the application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the drivers is approximated as Equation 38:
P = F sw ( 1.5V U Q + V L Q ) + P L + P U U L (EQ. 38)
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low switch charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET which has the drain-source voltage clamped by its body diode during turn-off, the high-side MOSFET turns off with VIN - VOUT, plus the spike, across it. The preferred low-side MOSFET emphasizes low r DS(ON) when fully saturated to minimize conduction loss. For the low-side MOSFET, (LS), the power loss can be assumed to be conductive only and is written as Equation 39:
P CON_LS I LOAD r DS ( ON )_LS ( 1 - D )
2
Where: Fsw is the switching frequency of the PWM signal VU is the upper gate driver bias supply voltage VL is the lower gate driver bias supply voltage QU is the charge to be delivered by the upper driver into the gate of the MOSFET and discrete capacitors - QL is the charge to be delivered by the lower driver into the gate of the MOSFET and discrete capacitors - PL is the quiescent power consumption of the lower driver - PU is the quiescent power consumption of the upper driver
(EQ. 39)
For the high-side MOSFET, (HS), its conduction loss is written as Equation 40:
P CON_HS = I LOAD r DS ( ON )_HS D
2
(EQ. 40)
For the high-side MOSFET, its switching loss is written as Equation 41:
V IN I VALLEY t ON F V IN I PEAK t OFF F SW SW P SW_HS = --------------------------------------------------------------------- + ----------------------------------------------------------------2 2 (EQ. 41)
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FN6707.0 August 14, 2008
ISL62871, ISL62872
Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off
Power Ground
Anywhere not within the analog-ground island is Power Ground. VCC and PVCC Pins Place the decoupling capacitors as close as practical to the IC. In particular, the PVCC decoupling capacitor should have a very short and wide connection to the PGND pin. The VCC decoupling capacitor should not share any vias with the PVCC decoupling capacitor. EN, PGOOD, VID0, and VID1 Pins These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. OCSET and VO Pins The current-sensing network consisting of ROCSET, RO, and CSEN needs to be connected to the inductor pads for accurate measurement of the DCR voltage drop. These components however, should be located physically close to the OCSET and VO pins with traces leading back to the inductor. It is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. The procedure is the same for resistive current sense. FB, SREF, SET0, SET1, and SET2 Pins
LOW-SIDE MOSFETS INPUT CAPACITORS
Layout Considerations
The IC, analog signals, and logic signals should all be on the same side of the PCB, located away from powerful emission sources. The power conversion components should be arranged in a manner similar to the example in Figure 17 where the area enclosed by the current circulating through the input capacitors, high-side MOSFETs, and low-side MOSFETs is as small as possible and all located on the same side of the PCB. The power components can be located on either side of the PCB relative to the IC.
GND OUTPUT CAPACITORS
+
+
VOUT PHASE NODE HIGH-SIDE MOSFETS VIN
FIGURE 17. TYPICAL POWER COMPONENT PLACEMENT
The input impedance of these pins is high, making it critical to place the loop compensation components, setpoint reference programming resistors, feedback voltage divider resistors, and CSOFT close to the IC, keeping the length of the traces short. LGATE, PGND, UGATE, BOOT, and PHASE Pins The signals going through these traces are high dv/dt and high di/dt, with high peak charging and discharging current. The PGND pin can only flow current from the gate-source charge of the low-side MOSFETs when LGATE goes low. Ideally, route the trace from the LGATE pin in parallel with the trace from the PGND pin, route the trace from the UGATE pin in parallel with the trace from the PHASE pin, and route the trace from the BOOT pin in parallel with the trace from the PHASE pin. These pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer.
Signal Ground
The GND pin is the signal-common also known as analog ground of the IC. When laying out the PCB, it is very important that the connection of the GND pin to the bottom setpoint-reference programming-resistor, bottom feedback voltage-divider resistor (if used), and the CSOFT capacitor be made as close as possible to the GND pin on a conductor not shared by any other components. In addition to the critical single point connection discussed in the previous paragraph, the ground plane layer of the PCB should have a single-point-connected island located under the area encompassing the IC, setpoint reference programming components, feedback voltage divider components, compensation components, CSOFT capacitor, and the interconnecting traces among the components and the IC. The island should be connected using several filled vias to the rest of the ground plane layer at one point that is not in the path of either large static currents or high di/dt currents. The single connection point should also be where the VCC decoupling capacitor and the GND pin of the IC are connected.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike.
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FN6707.0 August 14, 2008
ISL62871, ISL62872 Typical Performance Curves
100 95 90 REGULATION (%) EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 2 4 6 8 10 IOUT (A) 12 14 16 18 20 VIN = 12.6V VIN = 19V VIN = 8V 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 VIN = 12.6V -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 12 IOUT (A) 14 16 18 20 VIN = 19V VIN = 8V
FIGURE 18. EFFICIENCY AT VOUT = 1.1V
FIGURE 19. LOAD REGULATION AT VOUT = 1.1V
1.0 EN 0.8 0.6 REGULATION (%) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 12 IOUT (A) 14 16 18 20 VIN = 8V VOUT PGOOD VIN = 19V VIN = 12.6V SREF
FIGURE 20. SWITCHING FREQUENCY AT VOUT = 1.1V
FIGURE 21. START-UP, VIN = 12.6V, VOUT = 1.05V, LOAD = 10A
EN
EN
SREF SREF PGOOD PGOOD VOUT
VOUT
20s
FIGURE 22. START-UP INTO 750mV PRE-BIASED OUTPUT, VIN = 12.6V, VOUT = 1.05V, LOAD = 10A
FIGURE 23. SHUT-DOWN, VIN = 12.6V, VOUT = 1.05V, LOAD = 50m
21
FN6707.0 August 14, 2008
ISL62871, ISL62872 Typical Performance Curves (Continued)
EN VOUT
PHASE SREF PGOOD VOUT UGATE
10s
LGATE
FIGURE 24. SHUT-DOWN, VIN = 12.6V, VOUT = 1.05V, LOAD = OPEN-CIRCUIT
FIGURE 25. CCM STEADY-STATE OPERATION, VIN = 12.6V, VOUT = 1.0V, IOUT = 10A
15ADC VOUT IOUT +10AF PHASE 5ADC VOUT -10AF 5ADC
UGATE PHASE
LGATE
FIGURE 26. DCM STEADY-STATE OPERATION, VIN = 12.6V, VOUT = 1.0V, IOUT = 3A
FIGURE 27. CCM LOAD TRANSIENT RESPONSE VIN = 12.6V, VOUT = 1.0V
11ADC +10AF 1ADC IOUT VOUT -10AF 1ADC
VOUT
SREF
PHASE
VID0
VID1
FIGURE 28. DCM LOAD TRANSIENT RESPONSE VIN = 12.6V, VOUT = 1.0V
FIGURE 29. VID TO SREF RESPONSE VIN = 12.6V, VOUT = 950mV AND 1.05V, IOUT = 10A
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FN6707.0 August 14, 2008
ISL62871, ISL62872 Typical Performance Curves (Continued)
VOUT VOUT
SREF
SREF
VID0 VID0
VID1
VID1
FIGURE 30. SREF FALLING RESPONSE VIN = 12.6V, VOUT = 1.05V TO 950mV, IOUT = 10A
FIGURE 31. SREF RISING RESPONSE VIN = 12.6V, VOUT = 950mV TO 1.05V, IOUT = 10A
VOUT
SREF
VID0
VID1
FIGURE 32. VID TO SREF RESPONSE IN DCM VIN = 12.6V, VOUT = 950mV AND 1.05V, IOUT = 100mA
23
FN6707.0 August 14, 2008
ISL62871, ISL62872
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN) Rev 0, 5/08
1.80 A B 6 PIN 1 ID#
20 19 1 2
16X 0.40
6 PIN #1 ID
0.500.10 3.20 (4X) 0.10
12 11 10
9
TOP VIEW
VIEW "A-A"
0.10 M C A B 0.05 M C
4 20X 0.20 19X 0.40 0.10
BOTTOM VIEW
( 1.0 ) (1 x 0.70) SEE DETAIL "X"
0.10 C
C
MAX 0.55
BASE PLANE
SEATING PLANE 0.05 C
( 2. 30 ) ( 16 X 0 . 40 )
SIDE VIEW
C ( 20X 0 . 20 ) ( 19X 0 . 60 )
TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
24
FN6707.0 August 14, 2008
ISL62871, ISL62872 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
6 INDEX AREA 2X 2X 0.10 C
N
E
SYMBOL A
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
12 0.10 C
A1 A3
TOP VIEW
b D
0.15 2.55 1.75
0.20 2.60 1.80 0.40 BSC
0.25 2.65 1.85
5 -
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
C
E e L L1 N Nd
0.35 0.45
0.40 0.50 16 4 4
0.45 0.55
2 3 3
e PIN #1 ID 12 L1 NX L NX b 5 16X 0.10 M C A B 0.05 M C BOTTOM VIEW
Ne NOTES: 0
-
12
4 Rev. 4 8/06
(DATUM B) (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
3.00 1.80 1.40 1.40
2.20
0.90 0.40 0.20 0.50 0.40 10 LAND PATTERN 0.20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 25
FN6707.0 August 14, 2008

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